Symmetrical multiprocessing (SMP), a type of computing that uses more than a single processor, rests at one end of a continuum running from the tongue-twister Cache-Coherent Non-Uniform Memory Architecture (ccNUMA) to the less tightly coupled massively parallel processor systems and on to distributed systems such as Beowulfs, which are clusters of commodity, off-the-shelf PCs that are interconnected with a technology like Ethernet and run programs written for parallel processing.
Ironically, both the strength (speed) and weakness (lack of scalability) of SMP come from its most salient feature: shared memory. On the plus side, there's no need for message passing, and there are rarely unequal memory fetches, allowing SMP systems to communicate and synchronize more quickly than other parallel-processing systems. Note the qualifier rarely; there is one resource that isn't shared. In most SMP systems, each processor has its own cache memory. This more expensive static RAM is required because main dynamic RAM access is too slow to keep up with the speed of the processors.
This, however, leads to a cache coherency problem when an SMP processor needs to access an address that may already be stored in another processor's cache. The problem is solved in hardware. The desired address comes from the other processor's cache, rather than from main memory, and the value in the originating cache is invalidated.
Although this solution is fast, it still generates more overhead than that of a single-processor system, which is one reason the throughput of SMP systems isn't proportionally greater than that of single-processor systems. That is, the throughput of two processors is less than twice the throughput of a single processor, and the throughput of four processors is less than twice that of two processors.
For a limited number of processors, SMP still beats out the overhead required by other parallel architectures, making it the front-runner for applications that require a high degree of cooperation.
Shared memory also has an impact on coding. While there is no need to pass data among processors, it is necessary to avoid race conditions, in which the last processor to access and write out a data value overwrites the work of the other processors. There is a limit to how many SMP processors may share the operating system and the resources of a computer before memory and bus contention impose a law of diminishing returns: The upper bound for ordinary desktop SMP systems appears to be about eight processors. High-end SMP systems and modified SMP systems like ccNUMA are more scalable.
Essentially, ccNUMA systems are SMP systems that are broken into memory domains, with some memory less local than for pure SMP. For applications that aren't tightly coupled and naturally fall into domains, this may be perfect. Higher-end ccNUMA systems have been made to scale to as many as 64 nodes, with 128 processors. However, SMP systems aren't fault tolerant. If one processor goes down, cache coherency for the operating system and the user application are no longer guaranteed. It's likely that system and user variables are left in an unresolved state. There may be pointers with values that have no meaning. Eventually, one of the remaining nodes is likely to access something that will cause it to crash.
A combination of an operating system, a motherboard and processors must be configured to run SMP. In software, SMP is supported by most varieties of Unix, Linux 2.0 and above, Mac OS 9 and above, OS/2 Warp Server, Windows NT, Windows 2000 and XP. It isn't supported by MS-DOS, Windows 95 or Windows 98. Threaded applications that can take advantage of SMP include Microsoft Corp.'s BackOffice Suite, Lotus Notes and SQL database managers from Oracle Corp., Sybase Inc. and Informix Corp.
On the hardware side, SMP can be implemented in UltraSPARC, SPARCserver, Alpha and PowerPC architectures, and also by all Intel chips, including 486s and above.
Because Intel owns the Advanced Programmable Interrupt Controller (APIC) standard that's used for SMP, other CPU vendors, including Taipei, Taiwan-based Via Technologies Inc. and Sunnyvale, Calif.-based Advanced Micro Devices Inc., can't use it. Instead, they support the nonproprietary OpenPIC standard for Via's Cyrix 6x86 and AMD's K6 processors.