STOCKHOLM (02/10/2000) - Toshiba Corp. yesterday at the International Solid-State Circuits Conference in San Francisco unveiled a new architecture for its next-generation Rambus Inc. memory chips that will allow it to shrink the die size of the higher density chips by 8 percent, compared to current 144M-bit versions.
Scheduled to start shipping in the second quarter, the 288M-bit RDRAMs (Rambus Dynamic Random Access Memory chips) will allow for up to 512M bytes of RDRAM on each module for use in high-performance computers, according to a statement from Toshiba America Electronic Components Inc., one of the Japanese computer and electronics maker's U.S. subsidiaries.
Pricing will be made available when the chips start shipping, Toshiba said.
The 8 percent shrinkage of the die size will allow for more individual chips to be cut from each silicon wafer and should therefore result in lower manufacturing costs. The 288M-bit RDRAMs will be manufactured on Toshiba's 0.175 micron process technology, the company said.
Due mainly to higher costs associated with the Rambus architecture, RDRAMs to date have only attracted relatively few takers among the world's PC makers, although the memory interface technology allows for data transfer rates of up to 1.6G bytes per second, or two to three times as fast as today's commonly used 100MHz SDRAM (synchronous DRAM) chips.
Toshiba, in Tokyo, can be reached via the Web at http://www.toshiba.co.jp/.